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Electrical Engineering Department

Kundan Nepal
Kundan Nepal

Assistant Professor of Electrical Engineering
Dept. of Electrical Engineering
Bucknell University
Lewisburg, PA 17837
Phone: (570) 577-3799
Fax: (570) 577-1449
kundan.nepal@bucknell.edu

Kundan Nepal's Personal Page



Educational Background:
  • B.S., Trinity College,2002
  • M.S., University of Southern California, 2003
  • Ph.D., Brown University, 2007

Research Interests:

  • fault/noise tolerant circuit structures and architectures
  • nanometer digital VLSI system design
  • reliability analysis and verification of high-performance circuits
  • design automation methods for digital integrated circuits

Selected Publications: 

  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. Designing nanoscale logic circuits based on Markov random fields, JETTA, Journal of Electronic Testing, Theory and Applications, pp 255-266, Volume 23 ,  Issue 2-3, June 2007.
  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. Techniques for Designing Noise-Tolerant Multi Level Combinational Circuits, Proceedings of Design, Automation and Test in Europe, Nice, April 2007.
  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits, IEEE Micro, pp 19-27, Volume 26, Issue 5, Sept-Oct. 2006.
  • Hui-Yuan Song, Kundan Nepal, Iris Bahar, Joel Grodstein. Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1815-1830, Volume 25, Issue 9, Sept 2006.
  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. Optimizing Noise-Immune Nanoscale Circuits using Principles of Markov Random Fields, Proceedings Great Lakes Symposium on VLSI, Philadelphia, April 2006.
  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. Designing MRF based Error Correcting Circuits for Memory Elements, Proceedings of Design, Automation and Test in Europe, Munich, March 2006.
  • Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, Alexander Zaslavsky. Designing Logic Circuits for Probabilistic Computation in the Presence of Noise, Proceedings of Design Automatic Conference, Anaheim, June 2005.
  • Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein. Symbolic Failure Analysis of Complex CMOS Circuits due to Excessive Leakage Current and Charge Sharing ,  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 502-515, Volume 24, Issue 4, April 2005.